GaN LED with solderable backside metal

ABSTRACT

A light-emitting element ( 24 ) is disclosed. A light emitting diode (LED) includes a sapphire substrate ( 26 ) having front and back sides ( 33, 35 ), and a plurality of semiconductor layers ( 28, 30, 32 ) deposited on the front side ( 33 ) of the sapphire substrate ( 26 ). The semiconductor layers ( 28, 30, 32 ) define a light-emitting structure that emits light responsive to an electrical input. A metallization stack ( 40 ) includes an adhesion layer ( 34 ) deposited on the back side ( 35 ) of the sapphire substrate ( 26 ), and a solderable layer ( 38 ) connected to the adhesion layer ( 34 ) such that the solderable layer ( 38 ) is secured to the sapphire substrate ( 26 ) by the adhesion layer ( 34 ). A support structure ( 42 ) is provided on which the LED is disposed. A solder bond ( 44 ) is arranged between the LED and the support structure ( 42 ). The solder bond ( 44 ) secures the LED to the support structure ( 42 ).

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/303,277, entitled “GaN LED with Solderable BacksideMetal”, filed Jul. 5, 2001.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to the lighting arts. It isparticularly applicable to the fabrication of high-brightness galliumnitride (GaN) based light emitting diodes (LEDs) and LED arrays, andwill be described with particular reference thereto. However, theinvention also finds application in connection with other types of LEDsand in other LED applications.

[0003] With reference to FIG. 1, a conventional gallium nitride (GaN)based LED 10 includes thin layers of semiconductor material of twoopposite conductivity types, typically referred to as p-type layers 12and n-type layers 14. The layers 12, 14 are typically arranged in astack, with one or more layers of n-type material in one part of thestack and one or more layers of p-type material at an opposite end ofthe stack. The LED 10 includes a light-emitting p-n junction region 16arranged between the p-type layers 12 and the n-type layers 14. Thevarious layers of the stack are deposited on a substrate 18, such as asapphire substrate, by metal-organic vapor deposition (MOCVD), molecularbeam epitaxy (MBE), or another deposition technique. After deposition,the substrate is typically cut or diced to form a plurality of LEDpackages. Each package includes one or more LEDs and a portion of thesubstrate 18.

[0004] In operation, an electric current passed through the LED 10 usingelectrical contacts 19 is carried principally by electrons in the n-typelayer 14 and by electron vacancies or “holes” in the p-type layer 12.The electrons and holes move in opposite directions toward the junctionlayer 16, where they recombine with one another. Energy released by theelectron-hole recombination is emitted from the LED 10 as light 20. Asused herein, the term “light” includes visible light as well aselectromagnetic radiation in the infrared and ultraviolet wavelengthranges. The wavelength of the emitted light 20 depends upon manyfactors, including the composition of the semiconductor materials, thestructure of the junction 16, the presence or absence of impurities inthe junction 16, and the like.

[0005] GaN-based LEDs, such as the LED 10 shown in FIG. 1, are typicallyfabricated on sapphire substrates 18, through which substrate 18 lightcan be extracted from a substrate back side 21. Alternatively, it isknown to use a reflective layer 22 applied to the back side 21 of theLED 10. The reflective layer 22 reflects the emitted light 20 to producereflected light 23 that contributes to a front-side light output andimproves light extraction from the LED. Typically, the reflectivecontact is comprised of a single layer of aluminum or gold deposited onthe back side 21 of the substrate 18. Such a configuration isillustrated in U.S. Pat. No. 5,939,735 issued to Tsutsui et al.

[0006] GaN-based LEDs are conventionally attached to a lead frame or aheat sink using a die-attach epoxy between the back surface 21 or thereflective layer 22 and the lead frame or heat sink. A single aluminumlayer reflective contact on a GaN-based LED as proposed by Tsutsui onlyallows die attachment using an adhesive epoxy compound.

[0007] The use of epoxy to attach an LED die to a lead frame or heatsink causes problems. First, die-attach epoxies typically have a lowthermal conductivity resulting in a thermal resistance between theactive region of the LED and the heat sink of approximately 120° C./W.Such a high thermal resistance limits the amount of current and/or powerwhich can safely be applied to the LED without encountering failure dueto overheating or the like.

[0008] Second, epoxy compounds are subject to degradation whenilluminated by a blue or ultraviolet light produced by the LED. Thisdegradation is more pronounced at the elevated temperatures typicallyencountered in high-brightness GaN LED operation.

[0009] In view of the disadvantages of epoxies for connecting LED chipsto a heat sink, lead frame or the like, it would be preferable to employa solder connection. Solder connections typically exhibit a low thermalresistance of about 20° C./W and possibly as low as 5° C./W.Furthermore, there are several package configurations which areparticularly well-suited for soldering of the LED. Generally, reflectivelayers and/or contacts such as those proposed by Tsutsui and/or shown inFIG. 1 are incompatible with soldering because the aluminum does notprovide a good surface for solder bonding. Similarly, a gold reflectivelayer adheres weakly to the sapphire substrate, and so soldering to agold reflective layer typically results in delaminating of the goldlayer from the substrate.

[0010] The present invention contemplates an improved backsidemetallization and method for forming the same that overcomes theabove-mentioned limitations and others.

BRIEF SUMMARY OF THE INVENTION

[0011] In accordance with one embodiment of the present invention, Alight-emitting diode is disclosed. A stack of gallium nitride basedlayers is configured to emit light responsive to an electrical input. Alight-transmissive substrate has a front side and a back side. Thegallium nitride based layer stack is disposed on the front side. Thesubstrate is light-transmissive for the light produced by the galliumnitride based layer stack. A metallization stack includes a solderablelayer formed on the back side of said substrate. The metallization stack(i) reflects a portion of the light produced by the gallium nitridebased layer stack toward the front side of the substrate, and (ii)attaches the light-emitting diode to an associated support by a solderedbond.

[0012] In accordance with another embodiment of the present invention, alight-emitting element is disclosed. A light emitting diode (LED)includes a sapphire substrate having front and back sides, and aplurality of semiconductor layers deposited on the front side of thesapphire substrate. The semiconductor layers define a light-emittingstructure that emits light responsive to an electrical input. Ametallization stack includes an adhesion layer deposited on the backside of the sapphire substrate, and a solderable layer connected to theadhesion layer such that the solderable layer is secured to the sapphiresubstrate by the adhesion layer. A support structure is provided onwhich the LED is disposed. A solder bond is arranged between the LED andthe support structure. The solder bond secures the LED to the supportstructure.

[0013] In accordance with yet another embodiment of the presentinvention, A method is provided for fabricating a light-emittingelement. Semiconducting layers are deposited on a front side of anelectrically insulating substrate wafer such that the semiconductinglayers define a light-emissive region that emits light responsive to anelectrical current flowing therethrough. A metallic bonding layer isdeposited on a back side of the substrate. Electrical contacts areformed adjacent to selected semiconducting layers on the front side ofthe substrate. The metallic bonding layer is soldered to a supportstructure. The electrical contacts are connected to electrical inputsthat supply the electrical current to the light-emissive region.

[0014] In accordance with still yet another embodiment of the presentinvention, a light emitting diode (LED) is disclosed, including asubstrate and a stack of semiconductor layers arranged on a first sideof the substrate. The stack of semiconductor layers is configured toemit light responsive to an electrical input. A metallization stack isarranged on a second side of the substrate opposite the first side. Themetallization stack including a plurality of layers, said layersincluding at least: (i) a first layer formed from a first material thatadheres to the substrate, and (ii) a second layer formed from a secondmaterial that is suitable for solder bonding. The second material isdifferent from the first material.

[0015] Numerous advantages and benefits of the present invention willbecome apparent to those of ordinary skill in the art upon reading andunderstanding the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The invention may take form in various components andarrangements of components, and in various steps and arrangements ofsteps. The drawings are only for purposes of illustrating preferredembodiments and are not to be construed as limiting the invention.Further, it is to be appreciated that the LED drawings are not to scale.

[0017]FIG. 1 shows a front elevation view of a conventional GaN-basedLED.

[0018]FIG. 2 shows a front elevation view of a GaN-based LED having abackside metallization in accordance with an embodiment of the presentinvention.

[0019]FIG. 3 shows a method for fabricating a GaN-based LED inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] With reference to FIG. 2, a gallium nitride (GaN) based lightemitting element 24 includes a substrate 26 of sapphire, GaN, siliconcarbide (SiC), or another material and an LED including one or morep-type GaN layers 28 and one or more n-type GaN layers 30 arrangedthereon. The LED shown in FIG. 2 has a p-on-n configuration in which then-type layer or layers 30 resides between the p-type layer or layers 28and the substrate 26.

[0021] Alternatively, an n-on-p configuration (not shown) has one ormore p-type layers residing between one or more n-type layers and asubstrate. Optionally, either LED configuration may be employed.Furthermore, the layers 28, 30 can be formed from gallium nitride (GaN),aluminum nitride (AlN), indium nitride (InN), or ternary or quaternaryalloys thereof such as aluminum gallium nitride (Al_(x)Ga_(1-x)N) orindium gallium nitride (In_(x)Ga_(1-x)N). It is also contemplated toemploy an alloy of all three binary compounds AlN, GaN, and InN(Al_(x)In_(y)Ga_(1-x-y)N). Instead of a nitride-based semiconductor,other semiconductors such as silicon carbide, a phosphide-basedsemiconductor, or the like can also be used.

[0022] Whether a p-on-n or an n-on-p configuration is used, an activep/n junction region 32 is arranged between the n-type and p-type layers28, 30. In one suitable embodiment, the n-type and p-type layers 28, 30are arranged in direct contact, and the active p/n junction region 32 isdefined by a region of charge transfer that takes place at the interfaceof the layers 28, 30 due to the difference in conductivity type. Inanother suitable embodiment, the active p/n junction region 32 includesone or more quantum wells formed by low bandgap material such as indiumgallium nitride (In_(x)Ga_(1-x)N) or indium nitride (InN). Under aforward bias, holes and electrons enter the active p/n junction region32 from the p-type and n-type layers 28, 30 and radiatively recombinewithin the active p/n junction region 32 to produce light.

[0023] The semiconducting layers 28, 30, 32 are arranged on a frontside33 of the substrate 26. An adhesion layer 34 is located adjacent to abackside 35 of the substrate 26. The adhesion layer 34 is metallic, andis preferably made of silver, aluminum, or rhodium. The adhesion layer34 is suitably in a range of 30 nanometers to 1 micron in thickness, andis preferably about 200 nanometers.

[0024] A diffusion barrier 36 is deposited on the adhesion layer 34. Thediffusion barrier 36 is also comprised of metal, and is preferably atitanium, nickel, or platinum layer, or an alloy thereof. In addition,the diffusion barrier can be made up of two or more layers of differentmaterials, such as a titanium/nickel stacked diffusion barrier. Thediffusion barrier layer 36 is suitably in a range of 10 nanometers to100 nanometers for a platinum or titanium single layer, and ispreferably about 50 nanometers. For a nickel single layer, the diffusionbarrier 36 is suitably in a range of 100 nanometers to 1 micron, and ispreferably about 500 nanometers.

[0025] A metal-bondable or solderable layer 38 is deposited on thediffusion barrier 36. The solderable contact 38 is comprised of metal,preferably silver, gold, or tin. The thickness of the solderable layer38 is suitably in a range of 100 nanometers to 2 microns, and ispreferably a gold layer of around 100 nanometers.

[0026] The adhesion layer 34, the diffusion barrier 36, and thesolderable layer 38 together form a metallization stack 40 suitable forsoldering to a heat sink, lead frame, or the like. The diffusion barrier36 prevents undesirable alloying or intermetallic compound formationbetween the adhesion layer 34 (e.g., aluminum) and the solderable layer38 (e.g., gold). The diffusion barrier 36 prevents intermixing ofdifferent metals that results in the formation of unstableintermetallics between the adhesion layer 34 and the solderable layer38.

[0027] In a preferred embodiment, the metallization stack 40 is annealedafter deposition to improve adhesion and relieve stress. A suitableannealing schedule includes a 5 minute anneal at between 200° C. and400° C. in a nitrogen or air ambient. Those skilled in the art canmodify the annealing schedule to accommodate different metals orthicknesses, to reduce or prevent thermal degradation of the lightemitting element 24 during the anneal, and the like.

[0028] The adhesion layer 34 provides a strong attachment or bonding ofthe metallization stack 40 to the substrate 26. In addition, theadhesion layer 34 acts as a reflective layer that reflects light emittedby the active p/n junction region 32 and increasing the light emissionof the LED.

[0029] The solderable layer 38 provides a suitable surface for solderingto an associated support 42, such as a heat sink, lead frame, or thelike, by a solder bond 44 without compromising the LED. Moreover, thesolderable layer 38 provides a strong mechanical attachment and goodthermal conductance between the substrate 26 and the associated support42.

[0030] The metallic stack 40 can be constructed from variouscombinations of aluminum, titanium, nickel, platinum, silver, and gold.The choices of metals depends upon the type of substrate, and thecompatibility of the layers 34, 36, 38. For a sapphire substrate 26, apreferred embodiment of the metal stack 40 includes: an adhesion layer34 of aluminum about 200 nanometers thick; a diffusion barrier layer 36of a platinum/nickel bi-layer including a platinum thickness of about 50nanometers and a nickel thickness of about 500 nanometers deposited ontothe platinum; and, a solderable layer 38 of gold about 100 nanometersthick.

[0031] In another suitable embodiment for a sapphire substrate 26, themetal stack 40 includes: an adhesion layer 34 of silver about 200nanometers thick; a diffusion barrier layer 36 of a titanium/nickelbi-layer including a titanium thickness of about 50 nanometers and anickel thickness of about 500 nanometers deposited onto the titanium;and, a solderable layer 38 of gold about 100 nanometers thick. The useof a titanium/nickel barrier layer 36 is particularly advantageousbecause the titanium provides for better adhesion to the silver adhesionlayer 34.

[0032] The metallization stack 40 is preferably directly deposited ontothe sapphire substrate 26 in wafer form during the LED manufacturingprocess. The various layers of the metallization stack 40 are suitablydeposited onto the sapphire wafer by evaporation, sputtering,electroplating, stencil printing, screen-printing, or other depositiontechniques or combinations of techniques. It is to be understood thatthe deposition of the layers 34, 36, 38 are not necessarily allperformed using the same deposition technique. For example, evaporationcan be used to deposit the adhesion layer 34, diffusion barrier layer36, and a nucleating deposit of the solderable layer 38, followed by anelectroplating of the bulk of the solderable layer 38.

[0033] The wafer is suitably lithographically processed to define LEDmesas. Each mesa has a first contact 46 formed on top of and contactingthe p-type GaN layer 28, and a second contact 48 contacting the n-typeGaN layer 30 in an area which has been etched away to form the mesa.Alternatively, instead of forming a mesa, contact openings for accessingthe n-type GaN layer 30 can be etched through the p-type GaN layer 28and the active p/n junction region 32.

[0034] In a preferred embodiment for a GaN LED, the lithographic mesadefinition and contacts 46, 48 formation is performed, and the wafer isthinned in preparation for dicing, prior to deposition of themetallization stack 40, because the contacts processing temperature istypically substantially higher than the metallization stack 40deposition and annealing temperatures, and can thermally damage thestack 40. However, those skilled in the art can alter the order ofprocessing to accommodate particular situations. For example, if thecontacts 46, 48 are thermally sensitive, it may be preferable to depositthe metallization stack 40 prior to formation of the contacts 46, 48.

[0035] The wafer is diced or separated into individual chips which areimmediately ready for placement onto a heat sink or lead frame bysoldering to the metallization stack 40 without further processing. Itis not necessary to align a solder with a chip after the LEDmanufacturing process. Accordingly, each diced chip is readily andeasily attachable and inexpensive compared to traditional methods ofattaching LED chips to heat sinks or lead frames.

[0036] In a preferred approach, the solder is stenciled onto the heatsink or lead frame and the LED chips arranged on the solder. Thestenciled solder is arranged in pads substantially conforming with thesize and shape of the LED chips, and the solder is reflowed after chipplacement. Alternatively, the solder can be deposited onto themetallization stack 40, e.g. during the formation of the stack 40, andthe LED chip with solder applied is placed onto the heat sink or leadframe and the solder reflowed. Using either approach, it isadvantageously unnecessary to precisely align the chip with the solderbecause the reflow effectuates a self-alignment of the LED chip with thesolder pad.

[0037] With continuing reference to FIG. 2 and with further reference toFIG. 3, a suitable fabrication method 50 for fabricating LED chipsstarts with a substrate wafer 52, such as a sapphire wafer. Thesubstrate wafer 52 is preferably large enough to fabricate a largenumber of LEDs diced therefrom. In an epitaxial deposition step 54,semiconductor layers 28, 30, 32 are deposited onto the substrate wafer52 to form an epitaxial wafer 56. For a GaN-based LED, layers of binary,ternary, or quaternary alloys of GaN, InN, and AlN are suitablydeposited epitaxially using metalorganic chemical vapor deposition(MOCVD), molecular beam epitaxy (MBE), or the like.

[0038] The substrate wafer 52 is preferably processed prior to epitaxialdeposition using typical wafer cleaning or other pre-treatment such aschemical cleaning, in-situ thermal degassing and surface oxide removal,and the like. Similarly, suitable epitaxial crystal growth techniquessuch as employment of low temperature buffers or nucleation layers areoptionally employed during the epitaxial growth step 54. Typically, theconductivity types of the p-type and n-type layers 28, 30 areestablished by introducing selected dopants during the epitaxial growth54. Alternatively or additionally, the doping of the layers is modifiedafter the deposition using dopant diffusion or other techniques.

[0039] With continuing reference to FIGS. 2 and 3, the epitaxial 56wafer is processed to form the front side p- and n-type electricalcontacts 46, 48 in a step 58. These contacts are preferably fabricatedusing a sequence of lithographic patterning steps, insulator depositionsteps, and contact material deposition steps that define p-type andn-type contact pads 46, 48 that electrically communicate with the p-typeand n-type layers 28, 30, respectively, either directly or throughcontact vias. In one suitable lithographic process, the contactsformation step 58 includes lithographically defining mesas including thetopmost layer (e.g., the p-type GaN layer 28 in FIG. 2) and the activeregion 32, and an etched region around the mesa where the buried layer(e.g., the n-type GaN layer 30 in FIG. 2) is exposed for contacting.Alternatively, contact via openings can be etched through the topmostlayer 28 and the active region 32 to electrically access the buriedlayer 30.

[0040] Once the lithographic processing and contract formation step 58is completed, the wafer is preferably thinned from the backside. As isknown to those skilled in the art, backside thinning advantageouslyhelps in subsequent device dicing and improves device yield. Because thethinned wafer is more fragile than the unthinned wafer, the contactformation processing step 58 which typically includes substantial wafermanipulation is preferably performed prior to wafer thinning. However,it is also contemplated to thin the wafer prior to the contact formation58, or even prior to the epitaxial growth 54. For dicing usingmechanical scribing, the sapphire substrate is preferably thinned to areduced thickness of about 4 mils. For laser dicing, a larger finalthickness is preferable. For large-area devices and/or initially thinsubstrate wafers, it is also contemplated to omit the wafer thinningstep 60.

[0041] With continuing reference to FIGS. 2 and 3, the backsidemetallization 40 is preferably applied to the thinned wafer backside inmetallization steps 62, 64, 66, and annealed in a step 68, to produce aprocessed epitaxial wafer with solderable backside metal 70. Theadhesion layer 34 is first deposited in a step 62, followed bydeposition of the diffusion barrier layer 36 onto the adhesion layer 34in a step 64, and deposition of the solderable layer 38 onto thediffusion barrier layer 36 in a step 66, to form a processed epitaxialwafer with solderable backside metal 68. The metal deposition steps 62,64, 66 are suitably performed by a single deposition technique in asingle processing session. For example, a thermal- or electronbeam-evaporator having a plurality of source material crucibles can beused to successively perform the layer deposition steps 62, 64, 66 in asingle session.

[0042] Alternatively, the deposition steps 62, 64, 66 can be performedin two or more separate sessions. For example, the adhesion anddiffusion barrier layers 34, 36 are typically thin compared with thesolderable layer 38, and so a vacuum evaporator which deposits materialslowly but in a clean high-vacuum environment is suitably employed todeposit the thin adhesion and diffusion barrier layers 34, 36 in thesteps 62, 64. Subsequently, the wafer is transferred to anelectroplating apparatus capable of high deposition rates at a lowervacuum grade to apply the thick solderable layer 38 in the step 66. Insuch a deposition sequence, it is also contemplated to deposit a thinportion of the solderable layer 38 in the vacuum evaporator to protectthe surface and establish the interface between the diffusion barrierand solderable layers 36, 38 in the high-vacuum environment.

[0043] Those skilled in the art can select other deposition techniquesand sequences which are suitable for the thermal stability of thevarious metallic layers and interfaces, the types of metals beingdeposited, and the like. In a preferred embodiment, the metallizationstack 40 is annealed in the step 68 to improve adhesion and relievestress. A suitable annealing schedule for a metal stack on a sapphiresubstrate is 5 minutes at about 200° C. to 400° C. in a nitrogen or airambient. Those skilled in the art can optimize the annealing schedulefor selected metals and layer thicknesses, and may optionally omit theannealing step 68 altogether if the layers adhere suitably wellas-deposited.

[0044] In the method 50, the metallization stack is applied after theepitaxial growth step 54, since the epitaxial growth temperature istypically substantially greater than the temperatures employed in themetal deposition steps 62, 64, 66. If the metal stack 40 is depositedbefore the epitaxial semiconductor deposition 54, the high temperaturesduring epitaxy could for example drive solid state diffusion between theadhesion layer 34 and the solderable layer 38 in spite of the presenceof the diffusion barrier layer 36. Furthermore, the metal depositionsteps 62, 64, 66 should be performed after the wafer thinning step 60,which as discussed previously is preferably delayed as long as possibleto minimize yield reductions due to manipulation of the thinned wafer.

[0045] However, if the metal deposition steps 60, 62, 64 employ highertemperatures than the epitaxial semiconductor deposition step 54 orcould otherwise adversely affect the semiconductor layers, the epitaxialdeposition 54 is optionally performed after the thinning step 60 and themetal deposition steps 62, 64, 66. Alternatively, the epitaxy 54 can beinterposed between metal deposition steps 62, 64 or between metaldeposition steps 64, 66.

[0046] Furthermore, the semiconductor epitaxy step 54 can be performedin multiple sessions, with the thinning and/or metallization steps 60,62, 64, 66 or other wafer-level processing performed in-between. Thoseskilled in the art can select a suitable temporal sequence for themethod 50 or portions thereof which optimally accounts for the thermalstability of the various layers and layer interfaces, concerns aboutcross-contamination of the layers, and the like.

[0047] In the described embodiment of a GaN-based LED on a sapphiresubstrate wafer, the substrate wafer 52 is electrically insulativesapphire. In this case, both p- and n-type layers 28, 30 are typicallycontacted from the frontside, which for the p-on-n configuration of FIG.2 requires lithographically defining access through the p-type GaN 28and the active region 32 to the n-type GaN layer 30, e.g. by etchingmesas or contact openings. However, for other LEDs in which a conductivesubstrate wafer is employed, the backside metal stack 40 is suitablyused as a contact for the buried layer proximate thereto. Of course, inthis case the conductivity type of the conductive substrate should matchthe conductivity type of the adjacent layer. However, due to the largecontacting area between the backside metal stack 40 and the substrate,the specific contact resistance can be substantial while still providinga low total contact resistance.

[0048] The wafer is diced in a step 72 to separate individual LED chips74. The dicing is suitably performed using mechanical scribing or alaser saw, and preferably employs a translation stage to automate thedicing. The wafer thinning step 60 advantageously aids in fracturing ofthe substrate to improve device yield during the dicing step 72. Eachindividual LED die has front side p-type and n-type contacts 46, 48 anda back side including the metal stack 40.

[0049] In a step 80, each individual LED die is soldered onto the leadframe, a heat sink, printed circuit board, or other associated support42 which optionally also provides thermal dissipation for the LED. Thesapphire substrate 26, the deposited metal stack 40, and the solder bond44 provides a thermally conductive path from the heat-generatingsemiconductor layers 28, 30, 32 to the associated support 42, e.g. aheat sink.

[0050] As described previously, in a preferred approach the solder isapplied the heat sink or to the solderable layer 38, the LED die isplaced approximately into place on the associated support 42, and thesolder is reflowed, e.g. by application of a small amount of heating, toeffectuate the solder bonding and simultaneous self-alignment of the LEDdie on the solder bonding pad of the associated support 42. This ensuresthat the LED is precisely aligned with the solder pad to ensure a largearea of contact for heat transfer.

[0051] Electrical contacting of the n-type and p-type bonding pads to anelectrical power source is established in a step 82, e.g. using wirebonding, to produce a plurality of mounted LED devices 84.

[0052] Although in the method 50 each LED die is described as beingsoldered to a corresponding support 42, it is also contemplated tosolder a plurality of LED dice onto a single support. For an LED array,a large number of LED chips are suitably soldered onto a single printedcircuit board (pcb) that includes conductive traces to which the p-typeand n-type contact pads of the LED chips are wire-bonded in the step 82to power the LED array.

[0053] The invention has been described with reference to the preferredembodiments. Obviously, modifications and alterations will occur toothers upon reading and understanding the preceding detaileddescription. It is intended that the invention be construed as includingall such modifications and alterations insofar as they come within thescope of the appended claims or the equivalents thereof.

1. A light-emitting diode comprising: a stack of gallium nitride basedlayers configured to emit light responsive to an electrical input; alight-transmissive substrate having a front side and a back side, thegallium nitride based layer stack disposed on the front side, thesubstrate being light-transmissive for the light produced by the galliumnitride based layer stack; and a metallization stack including asolderable layer formed on the back side of said substrate, themetallization stack (i) reflecting a portion of the light produced bythe gallium nitride based layer stack toward the front side of thesubstrate, and (ii) attaching the light-emitting diode to an associatedsupport by a soldered bond.
 2. The light emitting diode as set forth inclaim 1, wherein the metallization stack further includes: an adhesionlayer directly adjacent to the back side of the substrate and secured tothe back side of the substrate and secured to the solderable layer toeffectuate a securing of the solderable layer to the substrate.
 3. Thelight emitting diode as set forth in claim 2, wherein the adhesion layeris comprised of a material selected from a group consisting of silver,aluminum, and rhodium.
 4. The light emitting diode as set forth in claim2, wherein the metallization stack further includes: a diffusion barrierlayer arranged between the adhesion layer and the solderable layer thatsubstantially prevents intermixing between the adhesion layer and thesolderable layer.
 5. The light emitting diode as set forth in claim 4,wherein the diffusion barrier layer is comprised of a material selectedfrom a group consisting of titanium, nickel, platinum, and alloysthereof.
 6. The light emitting diode as set forth in claim 4, whereinthe diffusion barrier layer includes: a first diffusion barrier layersecured to the adhesion layer; and a second diffusion barrier layersecured to the solderable layer.
 7. The light emitting diode as setforth in claim 6, wherein: the adhesion layer is a silver layer; thefirst diffusion barrier layer is a titanium layer; and the seconddiffusion barrier layer is a nickel layer.
 8. The light emitting diodeas set forth in claim 6, wherein: the adhesion layer is an aluminumlayer; the first diffusion barrier layer is a platinum layer; and thesecond diffusion barrier layer is a nickel layer.
 9. The light emittingdiode as set forth in claim 2, wherein the solderable layer is selectedfrom a group consisting of a gold layer and a silver layer.
 10. Alight-emitting element comprising: a light emitting diode (LED)including a sapphire substrate having front and back sides, and aplurality of semiconductor layers deposited on the front side of thesapphire substrate, the semiconductor layers defining a light-emittingstructure that emits light responsive to an electrical input; ametallization stack including an adhesion layer deposited on the backside of the sapphire substrate, and a solderable layer connected to theadhesion layer such that the solderable layer is secured to the sapphiresubstrate by the adhesion layer; a support structure on which the LED isdisposed; and a solder bond between the LED and the support structurethat secures the LED to the support structure.
 11. The light emittingelement as set forth in claim 10, wherein the support structure is alead frame or a heat sink.
 12. The light emitting element as set forthin claim 10, wherein the metallization stack further includes: adiffusion blocking layer disposed between the adhesion layer and thesolderable layer that substantially reduces intermixing between theadhesion layer and the solderable layer.
 13. The light emitting elementas set forth in claim 12, wherein: the adhesion layer is an aluminumlayer, the diffusion blocking layer includes platinum and nickel, andthe solderable layer is a gold layer.
 14. The light emitting element asset forth in claim 12, wherein: the adhesion layer is a silver layer,the diffusion blocking layer includes titanium and nickel, and thesolderable layer is a gold layer.
 15. The light emitting element as setforth in claim 10, wherein: the adhesion layer is selected from a groupconsisting of an aluminum layer, a silver layer, and a rhodium layer.16. The light emitting element as set forth in claim 10, furtherincluding: front-side p-type and n-type contacts by which the electricalinput is applied to the semiconductor layers defining the light-emittingstructure.
 17. The light emitting element as set forth in claim 10,wherein the plurality of semiconductor layers are selected from a groupconsisting of GaN, AlN, InN, and alloys thereof.
 18. (Canceled) 19.(Canceled)
 20. (Canceled)
 21. (Canceled)
 22. (Canceled)
 23. (Canceled)24. (Canceled)
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 26. (Canceled)
 27. (Canceled) 28.(Canceled)
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 30. (Canceled)
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 32. A lightemitting diode (LED) comprising: a substrate; a stack of semiconductorlayers arranged on a first side of the substrate, the stack ofsemiconductor layers configured to emit light responsive to anelectrical input; and a metallization stack arranged on a second side ofthe substrate opposite the first side, the metallization stack includinga plurality of layers, said layers including at least: (i) a first layerformed from a first material that adheres to the substrate, and (ii) asecond layer formed from a second material that is suitable for solderbonding, the second material being different from the first material.33. The LED as set forth in claim 32, wherein the metallization stackfurther includes: a third layer interposed between the first and secondlayers and substantially reducing intermixing of the first and secondmaterials.